This invention relates to resistively heated microemitter arrays, particularly to the incorporation of sample-and-hold, and snapshot circuitry into read-in-integrated-circuits (RIICs) for use with microemitter arrays.
Infrared (IR) scene generation is presently a critical technology for testing of IR imaging systems, for example in IR-guided missile systems. By artificially generating a changing IR scene and projecting it into the IR sensing system of a missile, the various performance elements of the missile can be evaluated in a laboratory setting, reducing the need for costly missile test firings. This same IR scene generation technology is also being adapted for portable field testing of missiles and FLIR (Forward Looking InfraRed) systems.
Two-dimensional arrays of resistively heated microemitter elements are one type of device used to create and display infrared scenes. A microemitter element is generally a small two-terminal thin film resistor, that is deposited onto a thin silicon nitride or silicon dioxide substrate, that is supported from a base structure by thermally insulating legs or posts that also typically provide electrical connections to supply current to the element. Fabrication typically employs micromachining technology.
To simulate an entire IR scene, it is desirable to integrate the microemitter elements into a two-dimensional array. For adequate resolution, the array typically contains at least 512 elements in each of the x and y dimensions. FIG. 1A is a perspective view illustrating for clarity a 3xc3x973 array segment 100 of microemitter elements 102. For this configuration, two electrical connections 104 are provided to each element. For example, an array segment 100 of 3xc3x973 =9 elements 102 requires eighteen electrical connections 104. Extrapolating the 3xc3x973 array example to an array of 512xc3x97512 elements would produce a requirement for 524,288 electrical connections.
Emitted infrared power increases monotonically with increasing temperature. An electrical current through a specific emitter element 102 determines its temperature and therefore the infrared power that it emits. A single element 102 thus provides a single pixel (spatial resolution element) of an IR scene. By performing this process with every individual element 102 in an array, an infrared scene is generated pixel by pixel. The scene can then be updated at high speed to simulate a moving target that can be viewed by a remote IR imaging system.
A typical 512xc3x97512 microemitter array measures on the order of 30 mm on a side. Each emitter element 102 typically measures tens of microns on a side and has a dynamic range of several hundreds of degrees C. The temperature of the emitter element is proportional (to first order) to the power dissipated in the element. Therefore emitter element temperature has the same relationship as does the emitter element power dissipation to applied signal voltage. To attain the needed output temperature range, the range of currents supplied to an emitter element must be capable of changing dynamically by more than four orders of magnitude.
After the applied current is removed, a resistive emitter element cools by radiation and by heat conduction and/or convection through a surrounding gas atmosphere and/or mechanical support structure. The time constant for heating and cooling is typically a few msec, and can be selected by specifying the mass (heat capacity) of the emitter and the thermal conductance of the structure and surroundings.
To facilitate the required multiple electrical connections to emitter elements 102, a read-in-integrated-circuit (RIIC) 106 is employed. This integrated circuit provides electronic timing and output signals to the emitter array, as well as electric interconnects and support structure for each emitter element 102. RIIC 106 typically employs CMOS technology, and includes signal multiplexing, control, and power circuitry (see for example Cole et al., xe2x80x9c512xc3x97512 WISP (Wide Band Infrared Scene Projector) Arrays,xe2x80x9d SPIE vol. 2741, Orlando, Fla., 1996, p. 83).
As shown in FIG. 1A, emitter elements 102 are supported on RIIC 106 by thermally insulating legs, which also provide electrical connections 104 to the resistor body 108 (large central thin film deposition) of emitter element 102. Emitted IR radiation is shown by arrows 110 from a representative resistor body 108. Slots between adjacent emitter elements 102 minimize thermal crosstalk (i.e., pixel signal distortion caused by interelement heat conduction). Electrical connectors 104 can contact RIIC 106 directly or can contact supporting structures attached to that substrate (see Cole et al., U.S. Pat. No. 5,600,148, Issued Feb. 4, 1997).
It is desired for RIIC 106 to provide a unique signal voltage specific to each emitter element 102, thus causing each element to emit a unique and controlled amount of IR radiation. This element-specific interface-circuitry is contained in a portion of RIIC 106 called a unit cell 112. For a large array of emitter elements 102, each supporting unit cell 112 typically is physically located directly beneath its respective emitter element 102.
FIG. 1B is a simplified block diagram of the major circuitry blocks associated with conventional RIIC 106. Analog signal data are received at an analog signal interface 140, and are distributed by an analog signal multiplexer 148 through column interconnect lines 114 to individual unit cells 112 as addressed by a column multiplexer 142 and a row multiplexer 144. Unit cells 112 are configured in a two-dimensional array of unit cells 150. Typically, analog signal interface 140 can consist of 32 or more parallel analog input lines, and analog signal multiplexer 148 can consist of 32 or more parallel multiplexers, each associated with one of a plurality of off-RIIC digital-to-analog converters (not shown).
FIG. 1C is a simplified schematic block diagram of the conventional RIIC circuitry of FIG. 1B, showing an expanded view of two unit cells 112, 113. Unit cells 112, 113 are configured identically and are located in the same column but in differing rows in array of unit cells 150. In the architecture illustrated, analog signal interface 140 includes 32 parallel signal input lines. Column multiplexer 142 addresses analog signal multiplexer 148, causing analog pixel data to load onto 32 parallel column interconnect lines 114. Then row multiplexer 144 provides an address signal on a row enable line 124, which momentarily closes a sample-and-hold switch 120, charging a sample-and-hold capacitor 116 to a signal voltage V1 in 32 representative unit cells 112 in a selected row. An appropriate combination of column multiplexers 142 and row multiplexers 144 provide addressing for other unit cells 112 in RIIC 106. Again, according to conventional system architecture, no more than 32 unit cells can be addressed simultaneously.
Sample-and-hold capacitor 116 in the 32 representative unit cells 112 of the selected row is connected between a circuit ground node 130 and an input terminal of a transconductance amplifier 126. The output terminal of transconductance amplifier 126 is connected to resistor body 108 of emitter element 102 through electrical connection 104. Thus voltage V1 on sample-and-hold capacitor 116 will give rise to a corresponding current 132 from transconductance amplifier 126 through emitter element 102, heating the emitter element and generating infrared radiation (see FIG. 1A). Current 132 will remain steady until the next row enable signal refreshes the charge on sample-and-hold capacitor 116 in the next frame cycle.
Prior emitter arrays that have been used for IR scene generation have updated their display information one line or a portion of a line at a time. A number of organizations (see for example Cole et al., SPIE 1996, cited above; Cole et al., xe2x80x9cRecent Progress In Large Dynamic Resistor Arrays,xe2x80x9d SPIE vol. 3084, Orlando, Fla., 1997, p. 59; and Pritchard et al., xe2x80x9cCurrent Status of the British Aerospace Resistor Array IR Scene Projector Technology,xe2x80x9d SPIE vol. 3084, Orlando, Fla., 1997, p. 73) have produced resistive emitter arrays. All of these arrays exhibit a problem of frame overlap inherent in display architectures that update one line at a time. This frame overlap means that at high frame rates, part of the display is showing an old frame, while the rest of the display is being updated with a new frame. This problem can create anomalous output, such as the display of the same simulated fast moving target in two distinct locations at the same time on the emitter array.
Traditionally, the only way that these prior arrays can be used without the potential for frame overlap is to provide a xe2x80x9cdeadxe2x80x9d time, during which no new data are sent to the emitter array. During this dead time, the remote imaging system under test must completely sample the image. The minimum dead time must be at least as long as the integration time of the imaging system under test. The maximum usable frame rate for the emitter array is then determined by the sum of the integration time of the imaging system under test and the minimum time required to completely update a new frame.
As an example, a microemitter array with a 100 frame per second update rate (i.e., 10 ms per frame) being used with an imaging system under test that has a 2 ms integration time can display frames no faster than one every 12 ms (83 Hz frame rate) without incurring frame overlap problems. Providing a xe2x80x9cdead timexe2x80x9d has the further disadvantages of requiring the imaging system under test to stop sensing or to discard data except during the xe2x80x9cdead time.xe2x80x9d This is generally unacceptable for an imaging system under test.
Another drawback of existing microemitter arrays is a nonlinearity of IR output as a function of signal voltage input. A fourth order relationship to input voltage has been reported (see Cole et al. SPIE 1997, cited above, pp. 63-65). This results in a highly nonuniform minimum displayable temperature difference (MDTD) or temperature step resolution corresponding to the least significant bits (LSBs) of the input datastream, depending on the magnitude of the signal within the dynamic range. Improved MDTD uniformity is needed.
Prior RIIC designs have required off-RIIC multiple parallel digital-to-analog converters, or DACs (32 or more for a 512xc3x97512 pixel RIIC) to achieve desired 16 bit accuracy at a needed minimum display rate of 120 Hz or more (see for example Cole et al. SPIE 1997, cited above, p. 59). Poor performance resulting from multiple DACs have prompted some organizations to forego all on-chip multiplexing of drive signals, opting instead for individual off-RIIC drivers for all 512 display lines (see Pritchard et al., SPIE 1997, cited above, p. 73). Improved digital-to-analog conversion is clearly needed.
Other resistive emitter arrays (see for example Cole et al. SPIE 1997, cited above, and Pritchard et al., SPIE 1997, cited above) suffer from local output dependent voltage variations in the return path for the emitter current. These voltage variations result from element-to-element differences in the emitter current that are the result of changes in the projected IR scene. Thus the specific voltage across an emitter and its output signal are dependent on the output level of neighboring pixels. This results in crosstalk (interelement pixel signal distortion) among neighboring emitter elements.
Crosstalk that results when current return contacts in nearby unit cells have less resistance between each other than to their common connection to an off-IC ground is well documented in the literature on resistive emitter arrays. Previous methods to solve the problem of output dependent emitter crosstalk fall into two categories: effect reduction and effect compensation. Attempts to reduce the effect consist of laying out internal multilayer metal xe2x80x9cground paths in both the x and y directions, so any radiance changes occur gradually in both directionsxe2x80x9d (see Cole et al. SPIE 1997, cited above). Because of this, the return path for current from different unit cells in an emitter array would be longer or shorter depending on the cell location in the array. However, even for a steady state scene, there are voltage differences for internal IC grounding depending on the location of the unit cell and the impedance of the line. Supporters of this approach have indicated that future development would include an additional metal layer to enhance grounding.
Compensation attempts consist of analyzing the emitter input signals line by line and then reducing or augmenting the drive signal to each emitter to correct in advance for scene dependent crosstalk.
A dual sample-and-hold architecture in each unit cell of a read-in-integrated-circuit (RIIC) allows maximum frame rate without frame overlap. Each unit cell contains two capacitors, a sample-and-hold capacitor and a snapshot capacitor. Analog pixel signals are updated sequentially in a first sample-and-hold capacitor, during the same time period in which an emitter element displays a pixel of a display frame in response to a stored analog signal voltage on an isolated second sample-and-hold capacitor. At the end of a frame time, after all unit cells are updated sequentially, a FRAME LOAD timing signal initiates a global enable signal that momentarily closes a switch between first and second sample-and-hold capacitors for all unit cells. This allows the signals on the two sample-and-hold capacitors to combine, thereby updating all emitter elements for the next display frame.
The emitter element is interconnected to the second sample-and-hold capacitor through an emitter driver. Configuring the emitter driver as a voltage-mode amplifier (generating a voltage output in response to a voltage input) provides the advantage of more nearly linear power dissipation in the emitter element in response to the stored analog signal voltage on the second sample-and-hold capacitor. Nonlinearity is approximately second order (quadratic) with a voltage mode amplifier, whereas response with previous transconductance amplifiers (generating a current output in response to a voltage input) is typically nonlinear to the fourth order.
In another embodiment, analog signal voltages are updated sequentially in a first sample-and-hold circuit, while an emitter element displays a pixel of a first display frame in response to a stored analog signal voltage in an isolated parallel second sample-and-hold circuit. After all unit cells are updated, the switches are reversed for the two parallel sample-and-hold circuits, displaying a pixel of a second display frame in response to an updated stored analog signal voltage in the first sample-and-hold circuit. The operation of the two parallel circuits alternates for each sequential frame.
Analog pixel signals are delivered to the respective unit cells sequentially through an analog data line connected to the output of a digital-to-analog converter (DAC). In some embodiments, the DAC is incorporated onto the same semiconductor substrate as the unit cell and the other elements of the RIIC. This results in a simplified interface to the RIIC and in an increased immunity to noise.
In some embodiments, the unit cell is configured to include a constant current source. This constant current source typically includes two appropriately biased p-channel transistors. One of the transistors supplies constant current, which is conducted as a heating current through the emitter element and as a difference current. The difference current represents the difference between the current supplied by the current source and the current flowing through the heating element. This configuration maintains a substantially constant overall current in the unit cell, thereby providing a constant power dissipation in the unit cell, independent from variations in emitter element current. Accordingly, the scene dependent crosstalk and the thermal stability of the entire system are substantially improved.
In some embodiments, A constant current source in the unit cell provides constant power dissipation and temperature, independent from variations in emitter element current, up to a predetermined constant current limit. For emitter element currents greater than the predetermined limit, an independent current source in the unit cell is automatically activated without involving external control logic.
In some embodiments, the current through the emitter element returns to an external ground plane through semiconductor substrate contacts. The external ground plane serves as a common ground terminal for all unit cells. Each individual emitter element current return circuit is contacted through a p+substrate contact, and is isolated from other emitter element return circuits by surrounding n-wells. The current path then passes through a series of doped epitaxial and bulk silicon layers to the external ground plane. This configuration eliminates any metal interconnects, which otherwise produce scene-dependent Ixc3x97R voltage drops in the return circuit, that adversely affect crosstalk.
Modular system architecture permits large area displays, 1024xc3x971024 emitter elements and larger, having high data throughput. All-digital signal and control logic interfaces provide versatile operation, wide dynamic range, and noise immunity.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings.